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rev. 1.1, apr. 13, 2005 1 p/n: pm0837 MX25L802 8m-bit [8m x 1] cmos serial flash eeprom general ? 8,388,608 x 1 bit structure 128 equal sectors with 8k-byte each - any sector can be erased 2048 equal segments with 512-byte each - provides sequential output within any segment single power supply operation - 3.0 to 3.6 volt for read, erase, and program operations latch-up protected to 100ma from -1v to vcc +1v low vcc write inhibit is equal to or less than 2.5v performance ? high performance - fast access time: 20mhz serial clock (50pf + 1ttl load) - fast program time: 5ms/page (typical, 128-byte per page) - fast erase time: 300ms/sector (typical, 8k-byte per sector) low power consumption - low active read current: 10ma (typical) at 17mhz - low active programming current: 10ma (typical) - low active erase current: 10ma (typical) - low standby current: 30ua (typical, cmos) minimum 100,000 erase/program cycle software features input data format - 1-byte command code, 3-byte address, 1-byte byte address 512-byte sequential read operation built in 9-bit (a0 to a8) pre-settable address counter to support the 512-byte sequential read operation auto erase and auto program algorithm - automatically erases and verifies data at selected sector - automatically programs and verifies data at selected page by an internal algroithm that automatically times the program pulse widths (any page to be programed should have page in the erased state first) ? status register feature - provides detection of program and erase operation completion. - provides auto erase/ program error report hardware features sclk input - serial clock input si input - serial data input so output - serial data output package - 28-pin sop (330mil) features
2 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 pin configurations symbol description cs chip select test(1) test mode select si serial data input so serial data output sclk clock input vcc + 3.3v power supply gnd ground du(2) do not use(for test mode only) nc no internal connection pin description 28-pin sop (330 mil) note: 1.test input is used for in-house testing and must be tied to ground during normal user operation. 2.du pin is used for in-house testing and can be tied to vcc, gnd or open for normal operation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc test du nc nc nc nc nc nc nc nc nc nc nc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc gnd vcc nc nc nc si so cs sclk nc nc nc nc MX25L802 general description the MX25L802 is a cmos 8,388,608 bit serial flash eeprom, which is configured as 1,048,576 x 8 internally. the MX25L802 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). spi access to the device is enabled by cs input. the MX25L802 provide sequential read operation on whole chip. the sequential read operation is executed on a segment (512 byte) basis. user may start to read from any byte of the segment. while the end of the segment is reached, the device will wrap around to the beginning of the segment and continuously outputs data until cs goes high. after program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified page locations will be executed. program command is executed on a page (128 bytes) basis, and erase command is executed on both chip and sector (8k bytes) basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion and error flag status of a program or erase operation. when the device is not in operation and cs is high, it is put in standby mode and draws less than 30ua dc current. the MX25L802 utilizes mxic's proprietary memory cell which reliably stores memory contents even after 100,000 program and erase cycles.
3 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 block diagram address generator memory array (2048 x 4096) page buffer y-decoder x-decoder data register si cs sclk clock generator state machine mode logic sense amplifier hv generator output buffer so
4 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 1-byte command code bit7(msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 3-byte address(0 to 0fffh) ad1: x x x x x a19 a18 a17 ad2: a16 a15 a14 a13 a12 a11 a10 a9 ad3: x x x x x x a8 a7 1-byte byte address(0 to 7fh) ba: xa6a5a4 a3a2 a1 a0 note: 1.x is dummy cycle and is necessary 2.ad1 to ad3 are address input data 3.ba is byte address command definition com- read status clear read sector chip page mand array read status id erase erase program (byte) 1st 52h 83h 89h 85h f1h f4h f2h 2nd ad1 x x ad1 x ad1 3rd ad2 ad2 x ad2 4th ad3 ad3 5th ba ba 6th x 7th x 8th x 9th x action n bytes output clear output start to start to load read out status status vendor erase at erase at n bytes until byte byte code cs cs rising data to cs goes until until rising edge buffer high cs goes cs goes edge until high high cs goes high & start to program note: a19 to a13=sector address a19 to a9=segment address
5 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 program /erase na na erase program na na ready/busy completion error error note1 1=error 1=error 1=ready 0=busy device operation 1.before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2.when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs falling edge. in standby mode, so pin of this lsi should be high-z. 3.when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next csb rising edge. when this command is sent, the device will continuously send out the status register contents starting at bit7. the clock to clock out the data is supplied by the master spi. bit 6,5,2,1 = reserve for future use. bit 4 = "1" -----> there is an error occurred in last erase operation. = "0" -----> there is no error occurred in last erase operation. bit 3 = "1" -----> there is an error occurred in last program operation. = "0" -----> there is no error occurred in last program operation. bit 0 ="1" -----> device is in ready mode. ="0" -----> device is in busy mode. command description (1) read array this command is sent with the 4-byte address (command included), and the byte address, followed by four dummy bytes sent to give the device time to stabilize. the device will then send out data starting at the byte address until cs goes high. the clock to clock out the data is supplied by the master spi. the read operation is executed on a segment (512 bytes) basis. if the end of the segment is reached then the device will wrap around to the beginning of the segment. (2) read status register (3) clear status register this command only resets erase error bit (bit 4) and program error bit (bit 3) . these two bits are set by on-chip state machi ne during program/erase operation, and can only be reset by issuing a clear status register command or by powering down vcc . if status register indicates that error occurred in the last program/erase operation, any further program/erase operation will be prohibited until status register is cleared. (4) read id this command is sent with an extra dummy byte( a 2-byte command). the device will clock out manufacturer code (c2h) and device code (35h) when this command is issued. the clock to clock out the data is supplied by the master spi. note 1:the initial value of bit7 is "1". bit7 will have "1" to "0" transit only after program/erase operation is completed. bit 7 will shift from "0" to "1" only after issued program/erase/clear status register command.
6 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 (5) sector/chip erase this command is sent with the sector address(a19~a13) when operating sector erase. the device will start the erase sequence after cs goes high without any further input. a sector should be erased in a typical of 300ms. the average current is less than 10ma. the chip erase operation does not require the sector address input but two extra dummy bytes are necessary. during this operation, customer can also access read status & read id operations. (6) page program this command is sent with the page number(a19~a7), and byte address(a6~a0), followed by programming data. one to 128 bytes of data can be loaded into the buffer of the device until cs goes high. if the end of the page is reached, then the device will wrap around to the beginning of the page. the device will program the specified page with buffered data(until cs goes high) without any further input. the typical page program time is 5ms. the average current is less than 10ma. during this operation, customer can also access read status & read id operations. (7) standby mode when cs is high and there is no operation in progress, the device is put in standby mode. typical standby current is less than 30ua. power-on state after power-up, the device is placed in the standby state with following status: the status register is reset with following status : bit 7 = "1" -----> refer to page 5 for detail. bit 6,5,2,1 = reserve for future use. bit 4 = "0" -----> erase error flag is reset. bit 3 = "0" -----> program error flag is reset. bit 0="1" -----> device is in ready state.
7 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 address sequence the address assignment is described as follows : ba: byte address bit sequence: x a6 a5 a4 a3 a2 a1 a0 ad1:first address bit sequence: x x x x x a19 a18 a17 ad2:second address bit sequence: a16 a15 a14 a13 a12 a11 a10 a9 ad3:thrid address bit sequence: x x x x x x a8 a7 data sequence output data is serially sent out through so pin, synchronized with the rising edge of sclk, whereas input data is serially read in through si pin, synchronized with the rising edge of sclk. the bit sequence for both input and output data is bit 7 (msb) first, then bit 6, bit 5, ...., and bit 0.(lsb)
8 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 auto page program flow chart auto chip erase flow chart start f2h ad1 ad2 ad3 ba 83h dummy read status register data are written (until cs goes high) set page program command. set read status register command. to continue other operation, do clear status register command first. operation done, device stays at read status register mode until cs goes high. pgae program completed yes no no no bit7 = 0? bit3 = 0? program another page program error yes yes start f4h dummy dummy read status register to continue other operation, do clear status register command first operation done, device stays at read status register mode until cs goes high. chip erase completed no no no bit 7= 0? bit 4 = 0? erase error yes yes 83h dummy set read status register command. set chip erase command.
9 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 auto sector erase flow chart start f1h ad1 ad2 read status register to continue other operation, do clear status register command first. operation done, device stays at read status register mode until cs goes high. sector erase completed yes no no no bit7 = 0? bit4 = 0? erase another sector ? erase error yes yes 83h dummy set read status register command. set sector eraes command.
10 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 notice: 1.stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2.specifications contained within the following tables are subject to change. 3.during voltage transitions, all pins may overshoot to 4.6v or -0.5v for period up to 20ns. 4.all input and output pins may overshoot to vcc+0.5v while vcc+0.5v is smaller than or equal to 4.6v. rating value ambient operating temperature 0 c to 70 c storage temperature -55 c to 125 c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 10 pf vin = 0v cout output capacitance 10 pf vout = 0v maximum negative overshoot waveform 0v -0.5v 20ns maximum positive overshoot waveform 4.6v 3.6v 20ns
11 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 input test waveforms and measuresment level output loading device under test diodes=in3064 or equivalent cl +3.3v cl=50pf including jig capacitance 1.5v 0v note:input pulse rise and fall time are < 10ns ac measurement level 3.0v
12 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 symbol parameter notes min. typ max. units test conditions iil input load 1 10 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 10 ua vcc = vcc max current vin = vcc or gnd isb1 vcc standby 1 30 60 ua vcc = vcc max current(cmos) cs = vcc 0.2v isb2 vcc standby 1 3 ma vcc = vcc max current(ttl) cs = vih icc1 vcc read 1 10 30 ma f=20 mhz icc2 vcc program 1 10 30 ma program in progress current icc3 vcc erase current 1 10 30 ma erase in progress vil input low voltage -0.5 0.8 v vih input high voltage 2.0 vcc+0.5 v vol output low voltage 0.4 v iol = 500ua voh output high voltage 2.4 v ioh = -100ua dc characteristics (temperature = 0 c to 70 c, vcc = 3.0v ~ 3.6v) notes: 1. all currents are in rms unless otherwise noted. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation.
13 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 symbol parameter min. typ. max. units co nditions fsclk clock frequency 20 mhz tcyc clock cycle time 50 ns tskh clock high time 25 ns tskl clock low time 25 ns tr clock rise time 6 ns tf clock fall time 6 ns tcsa cs lead clock time 50 ns tcsb cs lag clock time 50 ns tcsh cs high time 100 ns tds si setup time 5 ns tdh si hold time 25 ns taa access time 30 ns tdoh so hold time 5 ns tdoz so floating time 0 20 ns tecy erase cycle time 300 1600 ms tpcy program cycle time 5 15 ms ac characteristics (temperature = 0 c to 70 c, vcc = 3.0v ~ 3.6v) serial data input/output timing si cs sclk so tcsb tcsh tdoz tr tf tskh tdh taa tdoh tds tskl tcyc tcsa bit 7 bit 7 bit 6 bit 0 bit 0 notes: 1. typical value is calculated by simulation.
14 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 standby timing waveform when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs falling edge. in standby mode, so pin of this lsi should be high-z. while cs=vih, current=standby current, while cs=vil and commands are issuing, or commands are invalid, current=5ma(typ.) to 15ma(max.). sclk si so 1st byte bit7 hi-z bit6 bit5 bit4 bit3 bit2 bit1 bit0 cs
15 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 read array timing waveform notes: 1. 1st byte='52h' 2. 2nd byte=address 1(ad1), a17=bit 0, a18=bit1, a19=bit2. 3. 3rd byte=address 2(ad2), a9=bit0, a10=bit1,......a16=bit7 4. 4th byte=address 3(ad3), a7=bit0, a8=bit1 5. 5th byte=byte address(ba), a0=bit0, a1=bit1,......a6=bit6 6. 6th-9th bytes for si ==> dummy bytes (don't care) 7. from byte 10, so would output array data cs sclk si so 1st data output byte 2nd data output byte 9th byte (dummy) cs sclk si so (n-1)th data output byte nth data output byte cs sclk si so 1st byte (52h) 2nd byte (ad1) bit7 hi-z hi-z bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit2 bit1 bit0 bit3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
16 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 read status register timing waveform notes: 1. bit 7=0 ==> program/erase completed 2. bit 4=1 ==>erase error 3. bit 3=1 ==>program error 4. bit 1,2,5,6 ==> reserve for future use 5. bit 0=1 ==> device is in ready state cs sclk si so 1st status output byte 2nd status output byte 2nd byte (dummy) cs sclk si so (n-1)th status output byte nth status output byte cs sclk si so 1st byte (83h) 2nd byte (dummy) bit7 hi-z hi-z bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit2 bit1 bit0 bit3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
17 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 cs sclk si so 1st byte (89h) hi-z bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 clear status register timing waveform notes: 1. 1st byte='89h' ==> clear status register 2. so at hi-z state
18 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 read id timing waveform notes: 1. 1st byte:85h. 2. 2nd byte:dummy byte. 3. 3rd byte:output manufacture code(c2h). 4. 4th byte:output device code(35h). 5. the 2 bytes id output will be wrap around. cs sclk si so 1st byte (85h) 1st id byte (c2h) hi-z cs sclk si so (n-1) id byte n id byte hi-z 2nd byte (dummy) 2nd id byte (35h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit0 bit7 bit6 bit0 bit7 bit6 bit0 bit7 bit6 bit3 bit2 bit1 bit0
19 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 auto page program timing waveform notes: 1. 1st byte:f2h. 2. 2nd byte:address ad1. 3. 3rd byte:address ad2 4. 4th byte:address ad3 5. 5th byte:address ba. 6. 6th byte:1st write data byte. 7. when the last byte of the page will be written, the byte address will be wrap around to the first byte of the page. cs sclk si so 1st write data byte 2nd write data byte 5th byte (ba) cs sclk si so (n-1)th wr ite data byte nth write data byte cs sclk si so 1st byte (f2h) 2nd byte (ad1) hi-z hi-z bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0
20 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 auto sector/chip erase timing waveform notes: 1. 1st byte:f1h for sector erase, f4h for chip erase. 2. 2nd byte:address ad1 for sector erase, dummy byte for chip erase. 3. 3rd byte:address ad2 for sector erase, dummy byte for chip erase. sclk si so 1st byte - f1h for sector erase - f4h for chip erase hi-z hi-z bit6 bit5 bit0 bit6 bit5 bit0 bit7 bit6 bit0 bit7 bit7 2nd byte - ad1 for sector - dummy for chip 3rd byte - ad2 for sector - dummy for chip cs
21 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 parameter typ.(1) max.(2) unit comments chip erase time 300 1,600 ms page programming time 5 15 ms excludes system level chip programming time 48 240 s overhead(3) erase and programming performance note: 1.typical program and erase time assumes the following conditions: 25 c,3.3v, and checker board pattern. 2.under worst conditions of 0 c and 3.0v. 3.system-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4.the maximum chip programming time is evaluated under the worst conditions of 0 c, vcc=3.0v, and 100k cycle with 90% confidence level. ordering information part no. access time operating standby package remark current current MX25L802mc-50 20mhz 10ma 30ua 28 pin sop (330 mil) MX25L802mc-50g 20mhz 10ma 30ua 28 pin sop pb-free (330 mil)
22 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 package imformation
23 p/n: pm0837 rev. 1.1, apr. 13, 2005 MX25L802 revision history revision no. description page date 1.0 1. remove "advanced information" title p1 mar/04/2003 1.1 1. added pb-free package p21 apr/13/2005
MX25L802 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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